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92595ha/63095th (ot) no. 4988-1/16 overview the lc74781 and LC74781M are on-screen display cmos lsis that display characters and patterns on a tv screen under microprocessor control. the lc74781 and LC74781M display up to 12 lines of 24 characters, each in a 12 18 dot matrix. features display structure: 12 lines 24 characters (up to 288 characters) character structure: 12 (horizontal) 18 (vertical) dots character sizes: three size settings each in the vertical and horizontal directions character set: 128 characters display start position: 64 position settings each in the vertical and horizontal directions blinking: in individual character units blinking types: two types with periods of about 0.5 and 1.0 second blanking: whole font area blanking (12 18 dots) background colors: 8 colors (in internal synchronization mode): 4fsc (ntsc/pal/pal-m/ pal-n) background colors: 4 colors (in internal synchronization mode): 2fsc (ntsc) background colors: 1 color (blue) (in internal synchronization mode): 2fsc (pal/pal-m/pal-n) external control input: 8-bit serial input format built-in sync separator circuit character blanked data output video output: compound ntsc, pal, pal-n and pal-m output package dimensions unit: mm 3067-dip24s sanyo: dip24s [lc74781] unit: mm 3045b-mfp24 sanyo: mfp24 [LC74781M] cmos lsi ordering number : en4988a lc74781, 74781m sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan on-screen display controller lsi for vcr products
pin functions no. 4988- 2 /16 lc74781, 74781m pin no. symbol function description 1 v ss 1 ground ground connection (digital system ground) 2 xtal in crystal oscillator connection used to connect the crystal oscillator and capacitor used to generate the internal 3 xtal out synchronization signal, or to input an external clock (2fsc or 4fsc). 4 ctrl1 crystal oscillator input switching switches between external clock input mode and crystal oscillator mode. low = crystal oscillator mode, high = external clock mode outputs the blank signal (the or of the character and border signals). (outputs a composite 5 blank blanking output sync signal when mod0 is high.) outputs the crystal oscillator clock during reset (when the rst pin is low), but can be set up to not output this signal by microprocessor command. 6 osc in lc oscillator connection connections for the coil and capacitor that form the oscillator that generates the character 7 osc out output dot clock. outputs the character signal. (functions as the external synchronization signal discrimination signal output pin when mod0 is high, and outputs the state of the judgment as to whether the 8 chara character output external synchronization signal is present or not. outputs a high level when the synchronization signal is present.) outputs the dot clock (lc oscillator) during reset, but can be set up to not output this signal by microprocessor command. 9 cs enable input serial data input enable input. serial data input is enabled when low. a pull-up resistor is built in (hysteresis input). 10 sclk clock input serial data input clock input. a pull-up resistor is built in (hysteresis input). 11 sin data input serial data input. a pull-up resistor is built in (hysteresis input). 12 v dd 2 power supply composite video signal level adjustment power supply pin (analog system power supply). 13 cv out video signal output composite video signal output 14 nc must be either connected to ground or left open. 15 cv in video signal input composite video signal input 16 v dd 1 power supply power supply (+5 v: digital system power supply) video signal input for the built-in sync separator circuit (used for either horizontal 17 syn in sync separator circuit input synchronization signal or composite sync signal input when the built-in sync separator circuit is not used.) 18 sep c sync separator circuit bias voltage built-in sync separator circuit bias voltage monitor pin built-in sync separator circuit composite sync signal output. (when mod1 is high, outputs a high 19 sep out composite sync signal output level during internal synchronization and a low level during external synchronization.) (outputs the syn in input signal when the internal sync separator circuit is not used.) 20 sep in vertical synchronization inputs a vertical synchronization signal created by integrating the sep out pin output signal. an signal input integrator must be attached at the sep out pin. this pin must be tied to v dd 1 if unused. the setting indicated by this pin takes priority in switching between the ntsc, pal, pal-m and 21 ctrl2 ntsc/pal-m switching input pal-n formats. a low level selects ntsc after a reset. the microprocessor command ntsc, pal, pal-m, or pal-n setting is valid. high = pal-m format. 22 ctrl3 sep in input control controls whether or not the vsync signal is input to the sep in input. low = vsync input, high = vsync not input. 23 rst reset input system reset input. a pull-up resistor is built in (hysteresis input). 24 v dd 1 power supply (+5 v) power supply (+5 v: digital system power supply)
pin assignment specifications absolute maximum ratings at ta = 25 c allowable operating ranges at ta = ?0 to +70 c note: if the xtal in pin is used in clock input mode, be sure to prevent input noise from becoming a problem. no. 4988- 3 /16 lc74781, 74781m parameter symbol conditions ratings unit maximum supply voltage v dd max v dd 1 and v dd 2 pins v ss ?0.3 to v ss + 7.0 v maximum input voltage v in max all pins v ss ?0.3 to v dd + 0.3 v maximum output voltage v out max blank, chara and sep out pins v ss ?0.3 to v dd + 0.3 v allowable power dissipation pd max ta = 25 c 350 mw operating temperature topr ?0 to +70 c storage temperature tstg ?0 to +125 c parameter symbol conditions min typ max unit supply voltage v dd 1 v dd 1 pin 4.5 5.0 5.5 v v dd 2 v dd 2 pin 4.5 5.0 1.27 v dd 1 v input high level voltage v ih 1 rst, cs, sin and sclk pins 0.8 v dd 1 v dd 1 + 0.3 v v ih 2 ctrl1, ctrl2, ctrl3 and sep in pins 0.7 v dd 1 v dd 1 + 0.3 v input low level voltage v il 1 rst, cs, sin and sclk pins v ss ?0.3 0.2 v dd 1 v v il 2 ctrl1, ctrl2, ctrl3 and sep in pins v ss ?0.3 0.3 v dd 1 v pull-up resistance r pu rst, cs, sin and sclk pins, applies to pins set 25 50 90 k by options. composite video input voltage v in 1 cv in pin: v dd 1 = 5 v 2.0 vp-p v in 2 syn in pin: v dd 1 = 5 v 2.0 2.5 vp-p input voltage v in 3 xtal in pin (in external clock input mode), 0.10 5.0 vp-p f in = 2fsc or 4fsc: v dd 1 = 5 v f osc 1 xtal in and xtal out oscillator pins (2fsc: ntsc) 7.159 mhz f osc 1 xtal in and xtal out oscillator pins (4fsc: ntsc) 14.318 mhz f osc 1 xtal in and xtal out oscillator pins (2fsc: pal) 8.867 mhz f osc 1 xtal in and xtal out oscillator pins (4fsc: pal) 17.734 mhz oscillator frequency f osc 1 xtal in and xtal out oscillator pins (2fsc: pal-m) 7.151 mhz f osc 1 xtal in and xtal out oscillator pins (4fsc: pal-m) 14.302 mhz f osc 1 xtal in and xtal out oscillator pins (2fsc: pal-n) 7.164 mhz f osc 1 xtal in and xtal out oscillator pins (4fsc: pal-n) 14.328 mhz f osc 2 osc in and osc out oscillator pins (lc oscillator) 5 10 mhz
electrical characteristics at ta = ?0 to +70 c, v dd 1 = 5 v unless otherwise specified note: 1. when the sync level is 0.8 v. 2. when the sync level is 1.0 v. timing characteristics at ta = ?0 to +70 c, v dd 1 = 5 0.5 v no. 4988- 4 /16 lc74781, 74781m parameter symbol conditions min typ max unit input off leakage current i leak 1 cv in pin 1 a output off leakage current i leak 2 cv out pin 1 a output high level voltage v oh 1 blank, chara and sep out pins: v dd 1 = 4.5 v, 3.5 v i oh = ?.0 ma output low level voltage v ol 1 blank, chara and sep out pins: v dd 1 = 4.5 v, 1.0 v i oh = 1.0 ma input current i ih rst, cs, sin, sclk, ctrl1, ctrl3 and sep in pins: 1 a v in = v dd 1 i il ctrl1, ctrl2, ctrl3 and osc in pins: v in = v ss 1 ? a operating current drain i dd 1 v dd 1 pin; all outputs: open, xtal: 7.159 mhz, 15 ma lc: 8 mhz i dd 2 v dd 2 pin: v dd 2 = 5 v 20 ma sync level v sn cv out pin v dd 1 = 5.0 v, * 1 0.70 0.82 0.94 v v dd 2 = 5.0 v * 2 0.91 1.03 1.15 v pedestal level v pd cv out pin v dd 1 = 5.0 v, * 1 1.31 1.43 1.55 v v dd 2 = 5.0 v * 2 1.53 1.65 1.77 v color burst low level v cbl cv out pin v dd 1 = 5.0 v, * 1 1.00 1.12 1.24 v v dd 2 = 5.0 v * 2 1.21 1.33 1.45 v color burst high level v cbh cv out pin v dd 1 = 5.0 v, * 1 1.63 1.75 1.87 v v dd 2 = 5.0 v * 2 1.84 1.96 2.08 v background color low level v rsl cv out pin v dd 1 = 5.0 v, * 1 1.47 1.59 1.71 v v dd 2 = 5.0 v * 2 1.68 1.80 1.92 v background color high level v rsh cv out pin v dd 1 = 5.0 v, * 1 1.99 2.11 2.23 v v dd 2 = 5.0 v * 2 2.19 2.31 2.43 v border level 0 v bk 0 cv out pin v dd 1 = 5.0 v, * 1 1.42 1.54 1.66 v v dd 2 = 5.0 v * 2 1.63 1.75 1.87 v border level 1 v bk 1 cv out pin v dd 1 = 5.0 v, * 1 1.99 2.11 2.23 v v dd 2 = 5.0 v * 2 2.19 2.31 2.43 v character level v cha cv out pin v dd 1 = 5.0 v, * 1 2.58 2.70 2.82 v v dd 2 = 5.0 v * 2 2.78 2.90 3.02 v parameter symbol conditions min typ max unit minimum input pulse width t w (sclk) sclk pin 200 ns t w (cs) cs pin (the period when cs is high) 1 s data setup time t su (cs) cs pin 200 ns t su (sin) sin pin 200 ns data hold time t h (cs) cs pin 2 s t h (sin) sin pin 200 ns one word write time t word 8-bit data write time 4.2 s t wt ram data write time 1 s
serial data input timing no. 4988- 5 /16 lc74781, 74781m
system block diagram no. 4988- 6 /16 lc74781, 74781m
display control commands the display control commands have a serial input format with 8-bit units. a command consists of a command identifier code in the first byte and data in the second and subsequent bytes. there are eight commands as listed below. ? command0: display memory (vram) write address setup command command1: display character data write command ? command2: vertical display start position and vertical character size setup command ? command3: horizontal display start position and horizontal character size setup command ? command4: display control setup command ? command5: display control setup command 2 command6: synchronization signal detection setup command 3 command7: display control setup command display control command table once written, the command identifier code in the first byte is stored until the next first byte is written. however, when the display character data write command (command1) is written, the lc74781/m locks into the display character data write mode, and another first byte cannot be written. when a high level is input to the cs pin, the lc74781/m is set to command0 (display memory write address setup mode). no. 4988- 7 /16 lc74781, 74781m first byte second byte command command identification code data data 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 command0 1 0 0 0 v3 v2 v1 v0 0 0 0 h4 h3 h2 h1 h0 (set write address) command1 1 0 0 1 0 0 0 at 0 c6 c5 c4 c3 c2 c1 c0 (write character) command2 1 0 1 0 vs vs vs vs 0 fs vp vp vp vp vp vp (set vertical display start position and 21 20 11 10 5 4 3 2 1 0 vertical character size) command3 1 0 1 1 hs hs hs hs 0 lc hp hp hp hp hp hp (set horizontal display start position 21 20 11 10 5 4 3 2 1 0 and horizontal character size) command4 1 1 0 0 tst ram osc sys 0 blk blk blk bk bk rv dsp (display control) mod ers stp rst 2 1 0 1 0 on command5 1 1 0 1 np np non int 0 0 0 bcl cb ph ph ph (display control) 1 0 2 1 0 command6 1 1 1 0 mod mod dis mut 0 rn rn rn sn sn sn sn (synchronization signal detection) 1 0 lin 2 1 0 3 2 1 0 command7 1 1 1 1 ex pd ex pd 0 0 0 vnp vsp msk msk egl (display control) 1 1 0 0 sel sel ers sel
? command0 (display memory write address setup command) first byte second byte note: the register states are all set to zero when the lc74781/m is reset with the rst pin. command1 (display character data write setup command) first byte no. 4988- 8 /16 lc74781, 74781m register content da0 to da7 register name state function note 7 1 6 0 command 0 identification code 5 0 set the display memory write address. 4 0 3 v3 0 1 2 v2 0 1 display memory address (0 to b hexadecimal) 1 v1 0 1 0 v0 0 1 register content da0 to da7 register name state function note 7 0 second byte identification bit 6 0 5 0 4 h4 0 1 3 h3 0 1 2 h2 0 display memory address (0 to 17 hexadecimal) 1 1 h1 0 1 0 h0 0 1 register content da0 to da7 register name state function note 7 1 6 0 command 1 identification code 5 0 set up display character data write. 4 1 3 0 2 0 1 0 0 at 0 character attribute off 1 character attribute on when this command is input, the lc74781/m locks into the display character data write mode until the cs pin goes high.
second byte note: the register states are all set to zero when the lc74781/m is reset with the rst pin. ? command2 (vertical display start position and vertical character size setup command) first byte second byte note: the register states are all set to zero when the lc74781/m is reset with the rst pin. no. 4988- 9 /16 lc74781, 74781m register content da0 to da7 register name state function note 7 0 6 c6 0 1 5 c5 0 1 4 c4 0 1 3 c3 0 character code (00 to 7f hexadecimal) 1 2 c2 0 1 1 c1 0 1 0 c0 0 1 register content da0 to da7 register name state function note 7 0 second byte identification bit 6 fs 0 crystal oscillator frequency: 2fsc 1 crystal oscillator frequency: 4fsc 5 vp5 0 (msb) 1 4 vp4 0 1 3 vp3 0 1 2 vp2 0 1 1 vp1 0 1 0 vp0 0 (lsb) 1 the vertical display start position is set by the 6 bits vp0 to vp5. the weight of bit 1 is 2h. if vs is the vertical display start position then: 5 vs = h (2 s 2 n vp n ) n = 0 h: the horizontal synchronization pulse period register content da0 to da7 register name state function note 7 1 6 0 command 2 identification code 5 1 set the vertical display start position and vertical character size. 4 0 3 vs21 0 1 second line vertical character size 2 vs20 0 1 1 vs11 0 1 first line vertical character size 0 vs10 0 1 vs21 vs20 0 1 0 1h per dot 2h per dot 1 3h per dot 1h per dot vs11 vs10 0 1 0 1h per dot 2h per dot 1 3h per dot 1h per dot
? command3 (horizontal display start position and horizontal character size setup command) first byte second byte note: the register states are all set to zero when the lc74781/m is reset with the rst pin. ? command4 (display control setup command) first byte register content da0 to da7 register name state function note 7 0 second byte identification bit 6 lc 0 an lc oscillator is used for the dot clock. selects the dot clock used in horizontal 1 a crystal oscillator is used for the dot clock. character display. 5 hp5 0 if hs is the horizontal start position then: (msb) 1 5 4 hp4 0 hs = tc (2 s 2 n hp n ) 1 n = 0 3 hp3 0 1 2 hp2 0 1 1 hp1 0 1 0 hp0 0 (lsb) 1 the horizontal display start position is set by the six bits hp5 to hp0. the weight of bit 1 is 2tc. tc: period of the oscillator connected to oscin/oscout in operating mode. no. 4988- 10 /16 lc74781, 74781m register content da0 to da7 register name state function note 7 1 6 0 command 3 identification code 5 1 set the horizontal display start position and horizontal 4 1 character size. 3 hs21 0 1 second line horizontal character size 2 hs20 0 1 1 hs11 0 1 first line horizontal character size 0 hs10 0 1 hs21 hs20 0 1 0 1 tc per dot 2 tc per dot 1 3 tc per dot 1 tc per dot hs11 hs10 0 1 0 1 tc per dot 2 tc per dot 1 3 tc per dot 1 tc per dot register content da0 to da7 register name state function note 7 1 6 1 command 4 identification code 5 0 display control 4 0 3 tstmod 0 normal operating mode this bit must be zero. 1 test mode 0 the ram erase operation requires about 2 ramers 500 s (it is executed in the dspoff 1 erase display ram (set to 7f hexadecimal) state.) 1 oscstp 0 do not stop the crystal oscillator and lc oscillator circuits. valid when character display is off in 1 stop the crystal oscillator and lc oscillator circuits. external synchronization mode. 0 sysrst 0 reset occurs when the cs pin is low, and 1 reset all registers and turn the display off. the reset is cleared when cs goes high.
second byte note: the register states are all set to zero when the lc74781/m is reset with the rst pin. ? command5 (display control setup command) first byte no. 4988- 11 /16 lc74781, 74781m register content da0 to da7 register name state function note 7 0 second byte identification bit 6 blk2 0 character display block full character size specification 1 video display block 5 blk1 0 1 changes the blanking size. 4 blk0 0 1 3 bk1 0 blinking period: about 0.5 s switches the blinking period. 1 blinking period: about 1.0 s 0 blinking off when blinking is specified for reversed 2 bk0 characters, the blinking will be between 1 blinking on normal character and reversed character display. 1 rv 0 reverse (character reversing) off 1 reverse (character reversing) on 0 dspon 0 character display off 1 character display on blk1 blk0 0 1 0 blanking off character size 1 border size full character size register content da0 to da7 register name state function note 7 1 6 1 command 5 identification code 5 0 display control 4 1 3 np1 0 1 switches between ntsc, pal, pal-m 2 np0 0 and pal-n 1 1 non 0 interlaced switches between interlaced and non- 1 non-interlaced interlaced displays 0 int 0 external synchronization switches between external and internal 1 internal synchronization synchronization np1 np0 0 1 0 ntsc pal-m 1 pal pal-n
second byte note: the register states are all set to zero when the lc74781/m is reset with the rst pin. 2 command6 (synchronization signal detection setup command) first byte no. 4988- 12 /16 lc74781, 74781m register content da0 to da7 register name state function note 7 0 second byte identification bit 6 0 5 0 4 bcl 0 background color present only valid with internal synchronization. 1 no background color (only the background level is set) 3 cb 0 outputs a color burst signal. only valid when bcl is high. 1 stops color burst signal output. 0 2 ph2 1 0 1 ph1 1 0 0 ph0 1 sample background color phase diagram for pal mode color burst * : when 2fsc ntsc is used phase 2 phase 1 phase 0 background color (phase) ntsc pal 0 0 0 p /2 * p /2 0 0 1 in phase * in phase 0 1 0 3 p /2 * p /2 0 1 1 p * p 1 0 0 3 p /4 3 p /4 1 0 1 p /4 p /4 1 1 0 7 p /4 p /4 1 1 1 5 p /4 3 p /4 + + + register content da0 to da7 register name state function note 7 1 6 1 command 6 identification code 5 1 synchronization signal control settings 4 0 3 mod1 0 sync separator circuit signal switches the sep out (pin 19) output 1 high level output during internal synchronization 0 pin 5: blank signal 2 mod0 pin 8: character signal switches the blank (pin 5) and chara 1 pin 5: composite synchronization signal (pin 8) outputs pin 8: external synchronization signal discrimination output signal 1 dislin 0 12 lines switches the number of display lines. 1 10 lines 0 mut 0 normal output switches cv out 1 cv in is cut and cv out is fixed at the pedestal level.
second byte note: the register states are all set to zero when the lc74781/m is reset with the rst pin. 3 command7 (display control setup command) first byte second byte note: the register states are all set to zero when the lc74781/m is reset with the rst pin. no. 4988- 13 /16 lc74781, 74781m register content da0 to da7 register name state function note 7 0 second byte identification bit 6 rn2 0 1 5 rn1 0 1 4 rn0 0 1 3 sn3 0 1 2 sn2 0 1 1 sn1 0 1 0 sn0 0 1 external synchronization signal detection control signal present to absent transition recognition setting for the sampling period when sync can not be detected consecutively in the horizontal synchronization signal period (1h). external synchronization signal detection control signal absent to present transition recognition setting for the sampling period when sync can be detected consecutively in the horizontal synchronization signal period (1h). rn2 rn1 rn0 number of times hsync detected 0 0 0 0 times 0 0 1 4 times 0 1 0 8 times 1 0 0 16 times sn3 sn2 sn1 sn0 number of times hsync detected 0 0 0 0 not detected 0 0 0 1 32 times 0 0 1 0 64 times 0 1 0 0 128 times 1 0 0 0 256 times register content da0 to da7 register name state function note 7 1 6 1 command 7 identification code 5 1 display control setup 4 1 3 ex1 0 mode1 setting output switches the sep out (pin 19) output 1 port data1 setting output 2 pd1 0 the output is set low. 1 the output is set high. 1 ex0 0 mode0 setting output switches the blank (pin 5) output 1 port data0 setting output 0 pd0 0 the output is set low. 1 the output is set high. register content da0 to da7 register name state function note 7 0 second byte identification bit 6 0 5 0 0 v falling edge detection switches v acquisition polarity when 4 vnpsel internal v separation is used in external 1 v rising edge detection mode. 3 vspsel 0 vsep: about 8.9 s (for ntsc) switches the internal v separation time. 1 vsep: about 17.8 s (for ntsc) 2 mskers 0 mask valid hsync and vsync mask release 1 mask invalid 1 msksel 0 3h (for ntsc) switches the vsync mask. 1 20h (for ntsc) 0 egl 0 border level 0 only (vbk0) switches the border level 1 border level has two stages (vbk0, vbk1) (only valid for blk0 = 0 and blk1 = 1)
display screen structure the display consists of 24 characters 12 rows. the maximum number of displayed character is 288. the maximum number of characters is reduced to less than 288 when the character size is enlarged. display memory addresses are specified as row (0 to 11 decimal) and column (0 to 23 decimal) addresses. display screen structure (display memory addresses) no. 4988- 14 /16 lc74781, 74781m
no. 4988- 15 /16 lc74781, 74781m composite video signal output level (internally generated level) cv out output level waveform (v dd 2 = 5.00 v) v dd 2 = 5.00 v output level output voltage [v] output voltage [v] v cha : character 2.70 2.90 v bk 1: border 2.11 2.31 v rsh : background color high 2.11 2.31 v cbh : color burst high 1.75 1.96 v rsl : background color low 1.59 1.80 v bk 0: border 1.54 1.75 v pd : pedestal 1.43 1.65 v cbl : color burst low 1.12 1.33 v sn : sync 0.82 1.03
lc74781, 74781m ps no. 4988- 16 /16 this catalog provides information as of feburuary, 1997. specifications and information herein are subject to change without notice. n no products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n anyone purchasing any products described or contained herein for an above-mentioned use shall: accept full responsibility and indemnify and defend sanyo electric co., ltd., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on sanyo electric co., ltd., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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